[jws]

This Intel R&D paper sums the technology up and has a picture that makes it clear what they are doing: http://www.intel.com/technology/silicon/integrated_cmos.htm

In a nutshell, the drain/source is a tall trace, the gate approaches from the side and climbs over the drain/source, covering it on three sides.

[ableal]

The good stuff (discretely linked from the press release) is here: http://newsroom.intel.com/docs/DOC-2032 . In particular, this PDF has color drawings of the devices, and SEM pictures: http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Detai...

It is as you said - instead of the gate controlling the flow in a shallow ditch (the old "2D" does have some depth ;-), they built up a pipe and the gate is the choke around it.

Well, that should help stem the pesky leakage current problems that plague the deep sub-micron technologies ...