[jaguar1878]

Power consumption and package pinout/motherboard simplification would be the main two benefits.

Latency in DRAM access is dominated by the controller logic on the CPU side (minority) and the bank access and amplification circuitry on the DRAM side (majority). Time of flight down the wires is fairly negligible.

Power draw for the interface does scale meaningfully with wire length though. Also, routing the 100+ signals (command, address, data, reference voltages) can be a challenge, especially if the package is constrained on pin count.

The tradeoff is that maximum RAM capacity is significantly reduced. Die can be thinned and stacked quite high, but the need to share command, address, data busses means signal integrity problems and increased power for the interface with no performance increase. Stacking die has yield issues as well, so cost rises faster than linear. And finally, power dissipation becomes a real issue, DRAM doesn't like getting too hot and the bottom of that stack is a long way from the heatsink.