[Nelson69]

No idea but I suspect the "unified" on chip memory is very very quick.

Some friends and I were BSing about the "pro" level parts, it you can graft 2 or 4 M1s together, use off chip RAM and then treat that onboard 16GB like cache? We're talking about some game changing stuff.

[rbanffy]

The Xeon Phi had up to 16GB of fast memory in the same package as the main die. IIRC, it could be used as memory or as cache for external memory (which was much slower).

If Apple integrates two more memory chips, it'll be able to power a pretty solid desktop or laptop.

On the performance, Rosetta is most likely doing JIT so that most of the time it's running native ARM code. It did this with PPC binaries and DEC had it for Alpha.

[95014_refugee]

As noted elsewhere, Roesetta doesn't JIT unless the AOT transpilation lets it down. Most apps are statically transpiled at installation time...

[ecnahc515]

That's (AOT transpilation) quite the interesting approach to the problem. No wonder it's so fast.

[kzrdude]

We could also entertain the idea that if they would find some instruction particularly hard to emulate - they could have added new instructions on their own chip to cover it.

[MrBuddyCasino]

> on chip memory is very very quick

It is not on-chip memory, the dies are separate, they're just in the same package. They seem to use standard LPDDR4 connectivity, so I don't think its actually faster. The "unified" bit seems to matter more: having a single address space for both CPU & GPU, but this is pure speculation. I don't know if AMD or Intel APUs do this too.

[alblue]

The fact they are on the same package means that the electrical signals have a lot less far to travel from memory to cpu, and therefore you don’t have the signal losses or interference from the board having to route memory lines externally.

As a result you would be able to drive a higher bandwidth because you don’t need to be as limiting with the transfer time of signals.

[MrBuddyCasino]

Or you could use less power for the same speed. Hard to tell what Apple did, without some detailed benchmarks. I suppose one could bench memcpy and derive the clock rate from that.

[Taniwha]

It's unlikely you're going to transfer data any faster - they're using commodity drams like anyone else - they will however be able to save a clocks's worth of latency here and there which is useful

[ACAVJW4H]

Didn’t Intel have a similar idea with Skylake? Those had very fast albeit smaller eDRAM die glued to the processor. It was dropped on subsequent generations.

[buildbot]

It’s actually still surprisingly relevant in terms of performance [1], and I see it as a precursor to the gigantic caches we are seeing in the latest chips.

[1] https://www.anandtech.com/show/16195/a-broadwell-retrospecti...

[Dylan16807]

It worked pretty well but Intel clearly never liked the idea. They only offered it on a couple low-end models even before dropping it.

[rsynnott]

My impression was that this may have been designed at Apple’ behest; certainly they were the major user. Older than Skylake, btw; Haswell had it.

[Geee]

It might make sense to use very fast SSD as the main memory and on-chip RAM as cache. Huge amounts of RAM make only sense if your disks are slow or your workload actually needs the whole RAM which is rare.

[tonyedgecombe]

I do wonder where Apple will go with the Mac Pro. I guess a lot depends on how well the existing model has been selling (which we don't know).