[elFarto]

I doubt it's a limit of the CPU. It might be a limit of the method used to connect the PCIe component to the CPU (the SCB bus on the PI IIRC).

The device tree file does contain the range of memory to use for the PCI BAR, could it be as simple as increasing that number (the last value of the 'ranges' item I think) and rebuilding it? Seems unlikely, but might be worth a go. I'm uncertain how much the device tree file is describing the actual setup of hardware, and how much is used to actually configure the hardware.

The larger issue might be the complete lack of I/O space. Again this could be added in the device tree file, but who knows if the underlying device even supports it.