[tlack]

You feed in Rust (a flavor called DSLX) or C++ and it generates code for your FPGA (in Verilog). You then upload this compiled "bitstream" to your FPGA and now you have something akin to a custom microprocessor, but running just your program.

[est31]

It looks really quite similar to Rust: https://github.com/google/xls/blob/main/xls/examples/dslx_in...

Note that there are differences though: Seems no type inferrence, for .. in, different array syntax, match arms delimitered by ";" instead of ",".

But it has a lot of the cool stuff from Rust: pattern matching, expression orientedness (let ... = match { ... }), etc.

Also other syntax is similar: fn foo() -> Type syntax, although something similar to that can be achieved in C++ as well.

[muizelaar]

Looks like the match arm difference is going away: https://github.com/google/xls/pull/127

[est31]

Very cool. TBH, Rust's match arm delimiter story is a bit weird. Sometimes you need to put a ",", sometimes you don't. And macro rules macros have ";" instead of ",".

[couchand]

> Sometimes you need to put a ",", sometimes you don't

The rule is pretty simple: if you have curly braces you don't need a comma (and rustfmt will drop it), if you don't have curly braces you need a comma.