[panpanna]

Writing this with good intentions, not trying to start a fight...

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There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy.

Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.

[adwn]

> you are probably a verilog/SV guy and not an experienced VHDL guy

Wrong on both counts.

Please, enlighten me, what's wrong with my code? Note that it's in VHDL-2008, and the async. reset is intentional.

> I also recommend you read on VHDLs 9-valued logic and why it was designed this way

My main issue with VHDL is not the IEEE 1164 std_(u)logic, although it really doesn't help that this de-facto standard type for bitvectors and numbers (via the signed/unsigned types) is just a second-class citizen in the language – as opposed to bit and integer, which are fully supported syntactically and semantically, but which have serious shortcomings.

[panpanna]

Inconsistent Boolean expressions + lack of familiarity with unsigned and how it is supported by the tools.

Nothing major, but in my books this is the difference between a Jr and a Sr designer. Nitpicking, yes. But the hardware business is like.

[adwn]

> lack of familiarity with unsigned and how it is supported by the tools

Do you mean this: "x <= to_unsigned(25, x'length);" ? Some tools, like Synopsys, allow "x <= 25;" here, but other tools, like ModelSim, do not. The VHDL-2008 standard does not allow "x <= 25;".

> Inconsistent Boolean expressions

Do you mean because I wrote "if rst ..." but later "if c = '0'..."? Come on, you're not nitpicking, you're trying to find issues where there are none. Fixating on such anal-retentive details does not make you a "Sr designer", it makes you a bad engineer.