[jlokier]

I added one small Verilog file to a Vivado project.

It froze the IDE for 45 minutes before I could do anything else.

This was on a beefy machine at AWS too, not some cheap home desktop thing.

That wasn't compiling, no synthesis, P&R, nothing.

There was no giant netlist I'd been working on either. Most of the FPGA was empty.

That was literally just adding a small source file which the IDE auto-indexed so you could browse the contents.

In Verilator, an open source Verilog simulator, that same source file loaded, completed its simulation and checked test results in less than a second. So it wasn't that hard to compile and expand its contents.

Vivado is excellent for some things. But the excellence is not uniform unfortunately. On that project, I had to do most of the Verilog development outside Vivado because it was vastly faster outside Only importing modules when they were pretty much ready to use and behaviorally validated.

[tails4e]

That's definitely an anomaly, I use vivado with ASIC code reguarly, very large designs and have not seen anything like this. I use vivado to elaborate and a analyse code intended for ASIC use as its better than other ASIC tools for that purpose. Once I'm happy with it in vivado, then I push it through design compiler, etc. Elaborating a deign that is 4 hours in DC synthesis is about 3 mins in vivado elaboration.