[alfalfasprout]

I mean, the problem is that in the FPGA world the tooling and synthesis languages are inextricably linked. HLS is an approach that, IMO, is also the completely wrong direction since a general purpose programming language like C/C++ won't map nicely to the constructs you need in FPGA design.

What we really need is a lightweight, open source toolchain for FPGAs and one or more "higher level" synthesis languages. I've always wondered if a DSL using a higher language like Python isn't a better way to do this. Rather than try to transpile an entire language, just provide building blocks and interfaces that can then be used to generate verilog/VHDL.

[bb88]

> What we really need is a lightweight, open source toolchain for FPGAs and one or more "higher level" synthesis languages.

nMigen: python based DSL to verilog translator

LiteX: Open source gateware

SymbiFlow: Open source verilog compiler + PnR tooling.

There a linux kernel running on liteX and a Risc V core running on an ECP5 running out on the internets.

A micropython version running on a risc V core and migen (earlier version of nMigen) can also be found here: https://fupy.github.io/

[jlokier]

> I've always wondered if a DSL using a higher language like Python isn't a better way to do this

Like this? http://www.myhdl.org/

[bb88]

nMigen for python is where it's at these days.

https://github.com/m-labs/nmigen