[ohazi]

You generally don't do small runs of chips, unless cost is no object. The NRE costs of getting the masks made, even on older processes like these are still comfortably in the $X00,000 range, blowing past $1 million pretty quickly if you need a process that isn't ancient. That's without design software licenses, which can be hundreds of thousands more.

So the minimum order quantity usually needs to be at least in the tens to hundreds of thousands of chips if you don't want each chip to be a sizeable chunk of that initial cost.

It would be really nice to get to the point where small batch chips were viable though. One aspect is cost -- if they could get the NRE cost down to, say, $20k - $50k, and the software licensing cost down to zero, that would open up a lot of options.

The other aspect is the "dark art" nature of the process kit and communicating with the fab. If everybody assumes that chip design is expensive, they're going to be reluctant to even talk to the fab to see what options are available. If they see a bunch of people building interesting things with this shuttle program, then all of a sudden the fab is going to see more business interest as people try to figure out if there's a way to make their project work.

[MayeulC]

There are cheap-ish multi-project wafers (MPW).

These organizations typically also gives access to software design tools. But that's still a sizeable investment. Last project I've worked on used a (more expensive than usual I think) GloFo 22nm technology. Price was around €9k/mm², 9mm² was the minimum area. Still much more accessible to academia than individuals or open source projects, but not out of the realm of a crowdfunding campaign.

There are multiple chips that ought to be open source, broadly available, and cheap: AV1 decoders, small FPGAs, Wi-Fi or SDR chips, TMPs, and other crucial pieces for security, DIY/open HW projects, and basic computer building blocks. Most interesting to me are chips that would allow novel applications that commercial ventures would never look at, like open, hackable p2p WiFi meshes, or emulators-on-a-chip, or other application-specific coprocessors (protein folding, etc).

[1] ttps://mycmp.fr/technologies/process-catalog/

[2] https://europractice-ic.com/

[namibj]

A while back I came up with the idea of an ultra-miniature quadro copter with asynchronous outrunner motors who's stators would most likely be sintered (with or without a ferromagnetic matrix) to handle the power density, and a simple tube-shaped rotor (though a squirrel cage style might be better).

I'm thinking 5-20 mm rotor diameter (3M-750k rpm transonic limit), or maybe even smaller.

The interesting part would be an analogue ASIC that decodes an external control signal modulated onto the microwave (via rectenna) or optical (solar cell/photodiode) "wireless power" beam.

Demodulation would first do naive rectenna-based AM demodulation, followed by a bandpass and FM demodulation, revealing 12 carriers corresponding to the 4 3-phase motors, which are just FM-demodulated to yield the H-bridge control signals.

These would primarily be one xx MHz PLL and 12 lower-frequency ones spaced 50-200 kHz (the FM subcarrier's bandwith (assuming narrow-band FM) is twice the maximum motor field frequency), starting as low as feasible while still being able to use AC-coupling liberally.

Also either some amplifiers for (potentially-overdriven) "linear" H-bridge operation or (NE555-like?) PWM chopper drivers to exploit the winding inductance for less-wasteful H-bridge operation.

Far too much to realize in discrete circuitry, but nothing really fancy beyond a parametric PLL design. And not really realistic for a μC, either, because of brown-out resilience and overall latency.

At least the polyphase induction motors are very easy to drive, compared to the typical 3-phase permanent magnet outrunner motors used in most multicopters.

Depending on how predictable the effects of some tuning parameters are, maskless litho could allow for chips to be tuned to measured electro-mechanical properties of these sintered motors, reaching optimal drive waveforms. And for digital circuits, hard-wired ROM (security/shelf life/radiation-hardness) for individual chips or even doping-controlled ROM for anti-readout private/secret key storage.

I expect a maskless double-patterning ArF+immersion process allowing NDA-free-usage to be "the" thing that would enable true state-of-the-art experimentation and true ASICs (where the prototype needs an ASIC to be more than a paperweight after some photoshoots and staged interactions).

Feel free to contact me/let me know if you'd like further discussion(s).

[phonon]

You don't need your own mask; you can share with other customers.

https://en.wikipedia.org/wiki/Multi-project_wafer_service

https://www.tekmos.com/products/asics/reducing-the-asic-nre

[ohazi]

Yes, this is what Google is doing with this project.

[phonon]

Yup, https://youtu.be/EczW2IWdnOM?t=3444

[cottonseed]

efabless already runs the shuttle service that Google and efabless are going to fund here. From the efabless home page:

> $70K, 20 WEEKS, 100 SAMPLES

Note quite $50K, but close.

[grandmczeb]

Skywater (the actual fab Google is using for this program) also runs their own shuttle program[1]. The cost isn't public, but it's reportedly in the range of 40-50k.

[1] https://www.skywatertechnology.com/mpw-fastshuttle/