[baybal2]

An anecdote, the Allwinner, the company that once made MP3 and MP4 player chips made once thunderously popular A10 SoC with just $1,000,000 USD (set as a condition of the investor.)

Though, I admit, making just any IC under $1m requires really knowing what you are doing. Not something for a team of green engineers, and engineers whose only experience was doing cookie cutter SoCs from hard macros.

[bsder]

Well, if you steal all the CAD tools, design is pretty cheap ...

EDA CAD tools are infuriatingly expensive. You can get a chip run on an older node (180nm or 250nm) for <$100K. Good luck finding a set of EDA CAD tools for under that per year.

[esmi]

I used xcircuit, magic and irsim in university to make plenty of ASICs at MOSIS. Many universities still do. One can even get the NCSU PDKs for MOSIS for free. Totally compatible with 0.18u http://opencircuitdesign.com/magic/

[bsder]

Magic is sorta okay as long as you stick to low-performance digital or very small analog transistor counts.

The problem is that most of the "interesting" circuits for old tech nodes have a significant analog piece or RF piece--generally either ultra-low power(nanoamps) or higher voltages(15V+) or higher frequencies (2GHz+).

Both the simulation models as well as the tools to extract parasitics are extremely weak (or non-existent) on the open source front for analog and RF circuitry.

[LargoLasskhyfv]

Does this apply to the formerly commercial Bravo3VLSI from the 80ies, now available for free & open-sourced as Electric from https://www.staticfreesoft.com too?

[bsder]

Yes, unfortunately.

Anything based around Magic has to run on an extremely simplified set of rules in order so that the tiling and stitching mechanisms that it uses don't get upset.

DRC and extraction are hard. They require line-sweep geometry engines of fairly significant sophistication. Extraction requires some notion of third dimension matching and/or analysis.

The problem is that Cadence will donate tools to practically any school but will take your firstborn if you're a company--and Cadence are one of the better companies in the EDA space. This cuts off any incentive for someone in academia to create a new VLSI tool.

Note the accepted papers at DAC 2020: https://www.dac.com/content/2020-dac-accepted-papers

Not a single mention of "DRC", "rule", or "extract." Even simulators are thin on the ground unless you include "quantum". You would think that extraction, DRC, RF simulation, etc. are all solved tasks, right? (I assure you that algorithms in these spaces that can exploit massive parallelism are quite rare and are very difficult to implement well) :(

We should be living in the time of massive GPU and cloud acceleration of these tasks, and yet ... nothing.

This tells you what research is getting funded.

(Edit: Sorry, Largo, for some reason your down comment isn't getting a reply button...)

Edit: Magic, in this context, refers to the VLSI layout tool. Most open source EDA systems default to Magic as the thing that you use to draw/interpret physical geometry. This is good code reuse, but bad in that you inherit all of its limitations.

[LargoLasskhyfv]

Thanks for the fast response. What do you mean by magic in this context, are you referring to the program mentioned by the GP, or 'magically' simplifying DRC etc. as offered by Electric?

edit: I wasn't even aware of https://www.dac.com/ -> one more fractal in the Tsundoku stack

edit: never mind :-)