[tverbeure]

1. Most higher capacity FPGA have a features called "partial reconfiguration" where you can reload a part of the FPGA with a new bitstream. This new part can usually come from anywhere (PCIe, SPI, ...)

2. RISC-V is a ISA. It's not an implementation. You can implemented it on FPGA or ASIC. When you implement a RISC-V on an FPGA, it will cost you between $2 and maximum a few $1000 in silicon. FPGA technology itself is something that can only reasonably be implemented in an ASIC. The initial cost of an ASIC can go anywhere from $100K (on a very old process) to multiple millions.