[BrainlingPdx]

Perhaps I'm misunderstanding your point, but hasn't AMD proven this wrong at this point? With a correctly architected interconnect you can absolutely do chiplet based general computation processors.

Again, I may be misunderstanding your point...but I think the chiplet future is here on some level.

[throwaway_pdp09]

And I may be wrong, and for sure chiplets are proven (for now) to be a very good way of doing things, but those chiplets in AMD chips are relatively decoupled[0]. They're very large and connected within themselves already. They can be expected to operate substantially independently[0]. While they do have to talk to each other to get memory, probably a lot, DRAM access is so slow that it swamps the overhead of inter-chiplet communication[0]. Shared L3 cache, that's another matter I dunno.

I took it you meant like much smaller components, like ALU from this supplier, DRAM controller from that supplier, cache from another supplier etc, all on separate chiplets, each having to go off-chiplet to speak to the others. I am sure[0] that would cost much power and performance.

[0] serious risk of n00b arse-speak happening here, beware.