[nindanaoto]

We made our original CPU&ISA emulator over TFHE. https://github.com/virtualsecureplatform/kvsp

Because we use chisel to write CPU and we also made LLVM backend for our original CPU, your idea is not so difficult although it may be very slow. Our original CPU is about 4K gates. The most difficult point is building memory because it is most slow part. We used TFHE's LHE mode for it and this is one of the novel points of our work.

(We didn't know about Shape CPU but it seems to be similar to FURISC, which is published and using libScarab.https://eprint.iacr.org/2015/699)

[mmastrac]

Interesting. FURISC looks like it cribbed a lot of ideas off ShapeCPU without referencing prior art. I find it hard to believe someone would be working on a libScarab-based CPU without seeing ShapeCPU as well.

Encrypted termination conditions were definitely in that implementation. The memory mux too.

[nindanaoto]

I'm also doubting that but before I knew Shape CPU, I believed because FURISC seems to be based on HEROIC, which is claimed to be the first processor emulation over homomorphic encryption. https://past.date-conference.com/proceedings-archive/PAPERS/... I think FURISC is more like HEROIC than ShapeCPU.

By the way, I feel sad for there is no publication of ShapeCPU. I guess that this is one of the causes of FURISC paper is lacking reference for ShapeCPU.

[mmastrac]

It looks like ShapeCPU originated around 2012 but only made it into posters, not papers. It's kind of a shame because I spent quite some time reproducing their work to confirm that it was viable, then building on top of it with HideCPU.

Lots of prior art in that implementation!

[nindanaoto]

Our original CPU, CAHP-emerald is 5 stage pipeline, super-scalar processor. Pipelining improved performance well. https://github.com/virtualsecureplatform/cahp-emerald