[jdsully]

You can't really divorce IPC from the process used, the amount of nested logic in each pipeline stage is a direct function of gate delay and therefore the manufacturing process. On one process I may be able to fit 10 stages while on another I could fit 20. It's quite likely Intel's IPC would be much better on TSMC's 7nm vs their current 14nm.

This is also a problem when moving designs to a new generation FPGA. You may find your current level of pipelining is no longer optimal and you should do more each cycle.

People seem to have this weird idea that IPC is unrelated to how things are manufactured.