[saagarjha]

Well, kinda. The architecture is minimal but I had a strong focus on orthogonality, a linear address space, and clean instruction decoding; so much so that I named it REGULAR ;) The ISA (https://github.com/regular-vm/specification) was specifically selected so that traditional control flow could be created with the use of only one temporary register (some take a bit of work; conditional branches decompose to branch islands for example).

[gumby]

Yeah I was being tongue in cheek. Your approach sounds great for encouraging people to think about and find solutions to specific issues.

MIX was, in theory, supposed really to be the opposite: so universal/generic that you'd ignore the language and focus on the lesson. Similar to the motivation for using Scheme in SICP. Obviously times have changed :-).

Sort of the difference between putting on eyeglasses to see the world better (MIX) or putting on eyeglasses to learn about how lenses work.