[eoerl]

the key issue when compared to Epyc is that this is mono-die, and not much faster (even with metrics straight from Ampere). Mono-die means that the die is huge, the yield is low, it's probably pretty expensive to produce (and the reason why they went for 32MB cache, well below Arm's recommendations, core count is a bigger seller than cache it seems). Unless they get massively better performance (they don't), this has no chance vs a multi-die solution which has a much better yield. Intel is cornered in a similar situation right now. The same applies to Graviton, this stands absolutely no chance in the long run.

Not saying that the future has to be multi-die, but if it is not, then it has to be way faster than the cheaper-to-manufacture competition.

[msandford]

Huge die doesn't really matter if you have the ability to suffer defects on it and still turn out a quality product.

If they put 100 cores on every die but only activate 80 of them then that means they can tolerate absolutely HORRIBLE per-processor yields and still make chips that work. Their yields could actually be BETTER than with chiplets because they can afford so many problems.

Not saying that this is true, BTW, just that it's theoretically and practically possible.

[shdh]

The larger the die the greater the likelihood of defects. Also the larger the number of defects per mm/sq.

[ksec]

>the key issue when compared to Epyc is that this is mono-die,

This die cost metrics is way overblown and its narrative is too narrowly focused. Especially on ARM Server where unit cost dynamics with ARM IP along with much higher margin on server CPU lower the multi die BOM benefits. And the same definitely does not apply to Graviton, which Amazon owns the whole stack.

[eoerl]

Amazon owns nothing, not the ARM IP nor the manufacturing chain (TSMC or Samsung most probably), in that field it's not a big player. It owns what it does with Graviton, that's pretty much it.

Else yield obviously counts, that's what stands in the way of this CPU having more cache or 160 cores, for what it's worth, so it has to count for something obviously. The multiple tiers in every cpu manufacturer line up is also a consequence of yield, so it's very much not a minor element of the equation

[shdh]

I disagree.

More chips per wafer results in more yield, less chips with potential flaws.

> Dr. Hansch’s research at Universitat Munchen for example, shows how as die size increases manufacturers realize an accelerating yield loss and thus accelerating manufacturing cost. Using their model, assuming best-case defect densities, AMD’s small chiplet approach achieves 90% yields vs. Intel’s 30%-40% yields from its large, monolithic die approach. [1]

[1] https://www.barrons.com/articles/amd-stock-can-gain-87-fund-...

[ksec]

Since you actually did some research and posted a link I will go along with those numbers.

>We estimate Intel’s total server die cost at $162 per good server chip while AMD costs about $108 per good server package.

EPYC is 8 Die + an IOD, assuming the massive IOD of ~420mm2 only cost $10 ( That is suggesting GF are selling 14nm / 12nm Wafer at ~$1.2K, even under the AMD WSA with GF would likely not be feasible ), that number suggest the cost per Compute die would be ($106 - $10)/8 = $12, which is again off by quite a bit. Compared to equivalent die size cost of Intel, which is not even accurate because intel do not require the 65%+ Gross Profit Margin from TSMC and it is on an older mature node. And its yield are too pessimistic, we do not have any numbers from Intel on defect per mm2, but taking a guess from Nvidia's massive ~800mm2 die isn't too far off.

So again, let's assume both of those numbers are "relatively" correct. Do you think $62 would matter for an Intel® Xeon® Platinum 8280 Processor with Recommended Customer Price of $10K? Or the same die they are selling at the lower end for $3K?

While it would definitely be good to have those $62 as profits, the reality is on the server market its advantage is relatively minimal.

The bulk of the benefits of Chiplet approach is that you can reuse one or two designs and have it deployed across the whole range of market from Server to Desktop. As design cost increases with Pure Play Foundry such as TSMC this is extremely important for Fabless Design company like AMD, it cost them hundreds of million per design variation. Intel would have that problem down the road but it is mostly migrated for now because all of their design and fabs are in house, and would not cost them as much.

And since the original post was specific to ARM and Server, which has a different market dynamics in cost, you have less R&D as compared to x86 market. In ARM you are paying for IP price on the N1 core and some Interconnect, and those cost of Spread among all ARM players. Hence the conclusion of Chiplet is everything isn't as clear cut and why I said it is too narrowly focused.

[baybal2]

ARM cores are tens of times smaller than X86, plus very likely they fab it on a more mature node

[floatboth]

No, no way the Neoverse N1 is tens of times smaller than Zen 2, maybe a little bit smaller. And both are on TSMC's latest process.