[thesz]

Smaller chips have better yield. As AMD's current chips are composed from several smaller ones (I believe two or three), each composite has better yield than one bigger of same real estate size.

So yes, they figured out how to produce cheaper solutions.

[dragontamer]

> As AMD's current chips are composed from several smaller ones (I believe two or three)

For EPYC, AMD is using nine chips: https://images.anandtech.com/doci/13561/amd_rome-678_678x452...

That's 1x I/O chip (kind of like a router), and 8x chips, each of which has 8x cores on it. Total for 64-cores / 128-threads across 8-compute chips, talking together through a central 1x I/O and Memory chip.

The I/O chip is the biggest for reasons: 1. Its made on a cheaper process. 2. It has worse performance than the compute chips. 3. Its required to be big because driving external I/O requires more power.

So the I/O chip can be made on a cheap / inefficient 14nm process, while the CPUs can be made on a more expensive 7nm process (maximizing clock rates, power-efficiency). The big I/O ports are going to eat up a lot of power regardless of 7nm or 14nm process, so might as well save money here.

[cma]

It also sets them up to go forward into EUV where shot noise is unavoidable. And they had a contract with global foundries to still buy some large amount from them at a worse process node, the chipper design let’s them use that for the IO die.