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by mlyle
2329 days ago
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When I hear "embedded ARM", I hear "Cortex M". All of Cortex M is in-order and only M7-- still somewhat exotic-- has a real cache (silicon vendors often do some modest magic to conceal flash wait states, though). Alignment requirements are modest and consequences are predictable. Etc. About the most complicated performance management thing you get is the analysis of fighting over the memory with your DMA engine. And even that you can ignore if you're using a tightly coupled memory... |
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