[variaga]

For processes >= 40nm, the number is the gate length of the transistor. For smaller processes, the number is (approximately) the equivalent gate length that would result in the same transistor density (transistors per mm^2) as if the gate length had been reduced to that size, assuming everything else was scaled proportionately.

The trick is, not everything else scaled proportionately. The gate lengths (mostly) stopped shrinking at around 34nm but other things kept shrinking, so the overall transistor density kept going up.

(And that assumes planar transistors. Things like FinFET or nanowire which make the transistor structure 3d instead of 2d further disconnect the gate length from the achievable density.)