[ajross]

> SPI is much easier to write correctly

I'm not sure that I buy that. A daisy chained SPI bus is a rats nest of configuration hassle and basically impossible to debug. You're trading hardware robustness for software complexity, and that's not always a win.

And as far as hardware messes: SPI doesn't synchronize anything beyond the bit level (modulo an out of band chip enable or reset, of course, which would work to "fix" an I2C device too), making shift/offset bugs a real danger.

Board-level digital interfacing is just hard. That's why we do it as little as possible and put everything on the SoC these days.

[Gracana]

There are so many buggy I2C devices out there, I wouldn't say you're gaining hardware robustness, either.