[simcop2387]

It's apparently UPI now[1], but they'll still need to do a lot of updating to the CPU and UPI to get the bandwidth of pci-e 4.0. Best info I can find[1] puts pci-e 4.0 x16 at around 64GB/s, and UPI at a max of 28GB/s on their best xeon cpus and fpgas. Having that kind of bottleneck at the chipset would make it nearly pointless since even pci-e 3.0 with a 16x link is 32GB/s.

[1] https://www.tomshardware.com/news/intel-stratix-10-dx-upi-cx...

[paulmd]

Chipset doesn’t run at x16 bandwidth, it gets 4 lanes of bandwidth. At least for consumer platform, but I doubt server runs anything significant off chipset. QPI/UPI may run faster between sockets but I don’t think chipset is a full speed link by any means.

Nominally QPI/UPI but those protocols are not hugely distinct from PCIe in general. AFAIK it’s basically PCIe but encrypted, so that nobody else can replicate their chipsets (like used to happen in the old days with nForce/etc).

Also your numbers are off, easy rule of thumb is that one PCIe 3.0 lane is one GB/s of bandwidth per lane. So 3.0x16 is 16 GB/s of bandwidth.

So it just needs 8 GB/s of bandwidth to run at 4.0x4 speeds.