I wonder how good images could be with modern DRAM. A 256MB DDR3 chip would theoretically have over 2 trillion pixels. Light sensitivity should be better too due to the smaller capacitors.
Decapping and testing this wont be difficult, meaning you understand how individual transistors are located on the die to reorder raw data into planar image. I wonder if this information can be recovered using some known patterns shown to such sensor then retrieving appropriate data and analyzing.
Another interesting thing is that for training neural networks for image recognition purpose information about location of individual pixels is not necessary at all.
> Another interesting thing is that for training neural networks for image recognition purpose information about location of individual pixels is not necessary at all.
Convolutions use the spatial information. I'm less sure whether attention-based approaches typically use it.
Capacitors on DRAMs are usually implemented as PN junctions, maybe even parasitic capacitance of a transistor is used. Photons hitting depletion region of PN junction decreasing it hence increasing conductivity.