Yes but it still needs to:
a) empty the write buffers into the cache, then
b) flush the current instruction stream (in case the CPU has already fetched and decoded instructions from the modified memory)
Doing this on every write (especially considering multiple possible virtual to physical mappings) is very expensive in terms of hardware - it's why some architectures (RISC-V for example) have explicit instructions to trigger these things
Doing this on every write (especially considering multiple possible virtual to physical mappings) is very expensive in terms of hardware - it's why some architectures (RISC-V for example) have explicit instructions to trigger these things