[al2o3cr]

The more-complex interface makes it possible to optimize performance with very fine adjustments - for instance, sufficiently-modern DRAM can be precharging one bank while also servicing data requests from an already precharged one. It can also help with specific data-access patterns: for instance, if the FPGA always reads a whole page then a single precharge could serve for many reads.

[jjoonathan]

If you want a giant ring buffer with deterministic low latency, manual refresh control is a godsend.