|
|
|
|
|
|
by musicale
2401 days ago
|
|
|
> “different cores can have different/stale values in their individual caches”. Different processes can certainly have different versions of the same state, different values for the same variable, and different values at the same virtual address. And what about virtual caches? Non-coherent cache lines? Moreover, even in the face of cache coherency you can still have race conditions. |
|
|
what do you mean? Either two caches agree on the content of a cacheline or one of the cacheline is marked invalid (and the stale content is irrelevant). There are components of a core that might not respect coherency, like load and store buffers and arguably registers, but not caches (on cache-coherent systems of course).
Virtually addressed caches are an issue and that's why they have fallen out of favor.