| FPGA Pro here. I checked out the README.md to see if I could pick up any tips. It is a good guide for a first time through, but I recommend also reviewing the Xilix documentation on this. There's Xilinx App Note 1165 [Circa 2013] which is getting long in the tooth but still valid:
https://www.xilinx.com/support/documentation/application_not... And, Chapter 5 in Xilinx User Guide 892 is "Source Management and Revision Control Recommendations"
https://www.xilinx.com/support/documentation/sw_manuals/xili... There is also a .gitignore example which can be helpful but is not geared towards a minimal file set without alot of tweaking:
https://www.xilinx.com/support/answers/61232.html A few words of warning here:
The documentation recommends using the write_project_tcl and write_bd_tcl scripts. I have experienced problems with both of these not faithfully recreating the .xpr and .bd files so exercise caution with them. A better approach is to avoid .xpr files and to use a non-project or scripted flow. If you have to use a Vivado project for some reason (I can think of a couple) then create and maintain tcl script to generate the project by hand. One can use the write_project_tcl to get started and then update it by copying the tcl generated by Vivado after each GUI operation out of the Vivado tcl console into the project generation script when making changes to the project one wants to keep. I have had the most problems with write_bd_tcl so I am now experimenting with just checking in the .bd file and setting the .bd extension to "binary" and various merge strategies in the .gitattributes file after several projects worth of frustration with the write_xx_tcl nonsense. Finally, take all other Xilinx recommendation of source files to check in with a grain of salt. The documentation recommends checking in way too much. I recommend sticking with the "Minimum Set of Source Files to Manage" with archival backups of all output products for critical tags (eg. releases) somewhere outside the VCS. |