| Thanks for your question. There are some different design decisions between Chisel and Clash (and one or the other may work better for you!). Chisel is an embedded domain specific language in Scala that uses added hardware primitives to build a circuit graph and emit FIRRTL IR. Clash is a Haskell derivative that (in my limited understanding) reads a Haskell program, but interprets it using hardware semantics, eventually emitting Verilog. They are both hardware description languages and not HLS (c-to-gates). The Chisel ecosystem is larger, currently. This is primarily due to UC Berkeley/SiFive projects (Rocket Chip RISC-V SoC generator, BOOM out-of-order processor, Hwacha vector accelerator, etc.). One meta-difference is FIRRTL. Chisel/FIRRTL is trying to be a hardware compiler framework, analogous to LLVM, but for circuits. Chisel is only the front-end. You can interface other front-ends with or write your own front-end for FIRRTL (currently Yosys can target FIRRTL IT for Verilog -> FIRRTL IR). You then have a simple circuit IR to Target, but get access to all the existing FIRRTL transforms and have a path to Verilog for FPGA/ASIC. Relatedly, you can inject custom FIRRTL transforms into the FIRRTL compiler (one example being to add run-time fault injectors: https://github.com/IBM/chiffre). All that said... Host language matters. If you're comfortable with Haskell (or Python), use what works! And for new/existing languages, targeting FIRRTL IR is an option. More resources: - https://clash-lang.readthedocs.io/en/latest/faq.html - https://stackoverflow.com/q/27472473/3870549 |