| Thanks for looking into Chisel! Great question! However, this is an incredibly difficult question to answer as it relies on comparing language power. Paul Graham's "Beating the Averages" essay gets into this with the "Blub Paradox" [^1]. (tl;dr: a programmer versed in one programming language can evaluate less powerful languages, but not more powerful languages.) The FIR filter example shown is parametric. Verilog is also parametric. However, Chisel, because it's embedded in Scala, gives you other programming paradigms/features that Verilog/VHDL do not have (or vendor tools do not support): object oriented programming, functional programming, parametric polymorphism, first class function support, etc. The example of the front page could, instead of taking a `Seq[UInt]`, take a type parameter and be parametric for an arbitrary Chisel datatype (`UInt`, `SInt`, `FixedPoint`, etc.). Something like this just isn't possible with Verilog/VHDL. Analogously, Python and assembly both can describe for loops, but there are better dimensions for comparison. Problematically, if shown advanced features like parametric polymorphism too early (e.g., on the front page of the website) potential users will get confused and turn away. If shown an example too simple, but recognizable, users will see no benefits. Alternatively, Chisel does address SystemVerilog pain points. Michael Taylor does a nice job of elucidating these in Section 5 of [^2]. As this question comes up a lot, I've tried to iterate on an answer on SO which may also be a useful read [^3]. If you have any suggestions on better ways to get this across, any feedback is welcome, too. [^1]: http://www.paulgraham.com/avg.html [^2]: http://cseweb.ucsd.edu/~mbtaylor/papers/Taylor_DAC_BaseJump_... [^3]: https://stackoverflow.com/questions/53007782/what-benefits-d... |