| Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though). Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there. Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would only see for mammoth design like Rocket Chip (generating MBs of Verilog). Nonetheless, we have some ideas on how to improve this via actual optimizations or meta-optimizations like grouping compiler transformations together that are safe to do so. We also are really trying to make the Verification easier. One of these is effort on better testing via "Testers2"[^3] (name is TBD). The second is on improving the readability of the generated Verilog, e.g., emission of case statements [^4], emission of else-if[^5] (now supported!), etc. If you have suggestions we'd be happy to take a look (code examples of "I got this, but I'd like that" would be a huge plus, too!). Regardless, thanks for taking the time to check it out. [^1]: https://github.com/chipsalliance/api-config-chipsalliance [^2]: https://github.com/chipsalliance/rocket-chip [^3]: https://github.com/ucb-bar/chisel-testers2 [^4]: https://github.com/freechipsproject/chisel3/issues/1198 [^5]: https://github.com/freechipsproject/firrtl/pull/1204 |