[tfmkevin]

HLS is real. I've talked with dozens of teams who have successfully used HLS tools such as Mentor's Catapult, Xilinx's Vivado HLS, and Cadence's Stratus for a wide range of ASIC and FPGA projects. They claim they saw compelling benefits in project schedules, architectural flexibility, and overall performance. However, HLS is still (IMHO) a "power tool" for competent digital designers, not a tool that enables a software designer to create hardware. There is too much hardware-specific expertise required to create good HLS-able code and to do the tradeoffs like pipelining, unrolling, memory architecture, etc etc etc.