[PAGAN_WIZARD]

Ive seen plenty of HDL written by people who are software engineers, it's not good. It seems to me most software engineers struggle with visualizing their behavioral code as a schematic and tend to write code that is not very synthesis friendly and overly convoluted. Not to mention most issues with hardware engineering cant be solved by a google search of how to do X in Verilog/VHDL, problems tend to be device specific which means you NEED to understand your tool chain and can't abstract away the code from from the implementation like you can with most high level software to the ASM/binary.

[rowanG077]

I have seen some code written by software engineers that was bad and also a lot that was good. They simply need to be taught how HDLs work which is conceptually simpler then something like C++.

I very much disagree that most issues are hardware specific. FPGAs all work the same way. What is different is the IP that can be ran on different FPGAs but that is generally a tooling problem not inherent to the problem domain.