[qaute]

To elaborate:

A single IC die (a "chiplet" when stacked on others) is made of a layer of transistors and wiring up to several hundred nanometers thick on top of a much thicker (several hundred micrometer) silicon wafer substrate.

Yep, stacking these dies ("chiplets") on top of one another is one form of 3D, and is definitely useful: IIRC, AMD's recent popular Ryzen 3000 line uses chiplets, and the Raspberry Pi's RAM chip is stacked on top the CPU (in a much cruder post-IC-manufacturing assembly process). The shorter distance between dies (compared to placing them in separate plastic packages on a PCB) can lead to maybe an order of magnitude improvement (in speed/power/etc). It's hard to stack more than a few layers.

The most ambitious form of 3D design (and the one most people probably think of) is multiple thin layers of transistors on a single die ("monolithic 3D"); this would give maybe another order of magnitude improvement. Monolithic 3D memory chips are becoming popular (V-NAND, etc), with the most recent at ~100 layers. Monolithic 3D CPUs are still an unsolved problem because they need different, more difficult process steps and better heatsinks (but we're close!).

[benj111]

"Raspberry Pi's RAM chip is stacked on top the CPU"

Fyi, I don't think this is done in the most recent Pi 4

[hinkley]

I can't imagine the kind of quality control you have to have to have to achieve a useful yield, performing a lithography operation one hundred times on the same piece of silicon.

[baybal2]

Even 3D NAND is not the honest monolithic 3D, as it uses edge bonding and not real metal layers for word lines

[floatboth]

Is HBM also stacked in layers? IIUC there's like four layers of memory on each HBM2 die

[Bayart]

Yeah it's 3D-stacked. 4 layers for HBM, 4 for HBM and 12 for HBM2E.

It's neat but really expensive, and I don't think the gains for RAM in that sort of designs are that big compared to computing cores outside of edge cases.

[Bayart]

Meant to say *8 for HBM2