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by deepnotderp 2482 days ago
The advantage would be interconnect energy and performance.

To an extent this has already happened with wafer scale integration, e.g. cerebras.

1 comments

The problem is the increase power usage of the additional caches that are necessary - modern CPUs already need a bunch of physically local caches in addition to the large L1/2/3/n caches because of timing of flowing electrons from A to B. At some point the benefit of larger single die becomes minimal. The moment that happens you benefit from making separate chips because of increased yield.