|
|
|
|
|
by PhilWright
2504 days ago
|
|
Maybe they only recently decided to target RISC-V but the ALU design does not cover all the functions needed. It is missing implementation of the shift instructions, for that they need a 32 bit 5-level barrel shifter. Plus they also need a comparison block which is quite complex on its own. Given the number of years it has taken to get to this point, if could be 2050 before it is working. |
|
Capacitor memory addressed with tubes seems a strange choice. DRAM is capacitor memory, of course. Atanasoff, who had a a sort of computer in 1939, had capacitor memory, but he had to use a drum rotary switch to address it.
Memory was the big problem in the early days. IBM had an electronic multiplier before WWII, and plugboard-programmed machines, but no good memory elements. (Just registers with motor driven wheels and clutches and contacts.) Pilot ACE had a delay line (slow, serial access), the Manchester Baby had a Williams tube (too expensive per bit, but random access), and the EDVAC had mercury tank delay lines (slow, serial access, and toxic). Whirlwind (1951) had the first core memory (expensive per bit, but got cheaper over time.)
Core would be a reasonable choice for a tube system. Addressing is XY, so you need O(sqrt(N)) tubes.
Memory was a million dollars a megabyte as late as 1970.