[willis936]

I found the studies that this video (17:15) uses to establis a real world DRAM BER.

https://tezzaron.com/media/soft_errors_1_1_secure.pdf

https://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf

You’ll note that the papers were published in 2004 and 2009, respectively.

Here is a paper from 2015 that paints a more accurate picture of hardware used today.

https://www.cs.virginia.edu/~gurumurthi/papers/asplos15.pdf

Apparently these studies have strange ways to present data and do not give straight “BER per bit per second”, which I would think is the most useful metric. Without spending all day learning the jargon of this specific field, I think I can conclude, at a glance, that DDR4 has a lower BER than DDR3. The numbers matter, and I don’t know how serious of an issue it is currently. Without that knowledge its impossible to speak on the efficacy of more proliferated ECC in DRAM.