Even with the mesh the number of hops is variable based on which core is requesting and the physical geometry of the chip. The cores right beside the IMC will have the lowest latency. See this diagram: https://en.wikichip.org/wiki/intel/mesh_interconnect_archite...
The main improvement is the max number of hops is log(n) instead N/2.
The main improvement is the max number of hops is log(n) instead N/2.