[mrpippy]

It's worth remembering that the storage architecture of T2-based Macs (like this MacBook Air) is very different from previous Macs and any PCs.

The T2 chip is an Apple ARM SoC running Darwin/XNU (basically a cut-down iOS). It connects to the Intel system using a variety of buses.

From a storage perspective, the T2 is the storage controller. It sits between raw NAND flash and the Intel system (connecting to the Intel with PCIe/NVMe). The T2 transparently encrypts all data stored on the NAND, using the factory-burned-in key.

Given this architecture, how would read speeds drop by 35% from one model to the next? I'm not sure--my first guess was that fewer NAND chips were being used, but teardowns show that both 2018 and 2019 models were using two chips. So same controller, same number of chips. Maybe the NAND is just slower? Or the T2 has less RAM, so it can cache less?

[wtallis]

> Given this architecture, how would read speeds drop by 35% from one model to the next? I'm not sure--my first guess was that fewer NAND chips were being used, but teardowns show that both 2018 and 2019 models were using two chips.

NAND flash is almost always packaged with a stack of several dies in each BGA package. Individual dies are typically 256Gb (32GB) or larger, and most manufacturers will stack up to 8 or 16 dies per package. So an SSD with two packages can easily vary from 128GB (2 packages x 2 dies per package x 256Gb per die) to 2TB (2 packages x 16 dies per package x 512Gb per die).

It's also possible for a single BGA package to have the NAND organized on one or more channels. Drives using larger form factors (eg. enterprise SSDs using 2.5"/15mm dual-PCB) will typically have each package connecting to only one of the SSD controller's channels, and often have multiple packages per channel. Consumer SSDs that need to minimize PCB footprint take the opposite approach, using eg. two packages connecting to two channels each to fully populate a low-end 4-channel SSD controller.

I don't know Apple's recent history of NAND choices, but it's possible they've switched from MLC (two bit per cell) to TLC (three bit per cell) NAND flash, which sacrifices performance for density and cost. They have probably moved to 3D NAND with a higher layer count, which can be a mixed bag for performance especially when the controller is not also upgraded. If they've moved to a higher per-die capacity for drives with the same total capacity, then a significant performance drop for lower-capacity models is expected.

[ksec]

>Given this architecture, how would read speeds drop by 35% from one model to the next? I'm not sure--my first guess was that fewer NAND chips were being used, but teardowns show that both 2018 and 2019 models were using two chips. So same controller, same number of chips. Maybe the NAND is just slower? Or the T2 has less RAM, so it can cache less?

It is very common, if not the norm to have SSD slower at lowest end capacity. Having 2 Chip shown in the tear down doesn't mean it has the same channels inside those package. My guess is that it is Dual Channel per package, and it is only running at 3 Channels on the 128GB SSD.

[rhinoceraptor]

It might just be newer, higher density NAND. It's cheaper, but slower and less reliable.