[justaaron]

point being: Control. Precise control over timing is required for deterministic temporal activities.

Removing precise control over timing from the language stack one uses to program FPGA's with is removing a desirable feature for many of their uses cases.

If one is interesting in glossing over all this abstraction, why is one wishing to use an FPGA at all?

I will reverse the question and say: "in which scenarios is someone hoping to avoid addressing precise timing constructs in FPGA programming?"

Obviously I'm not referring to clock propagation delay or quantum entanglement etc LOL I mean the intentional macro stuff wrt "timing"

[reitzensteinm]

Parent was referring to clock propagation delay (resulting in multiple clock domains on the same chip), hence my confusion.

If you're talking about higher level timing, nobody is arguing for taking that away from you.

[justaaron]

I agree. I've seen System-Verilog used for simulating such propagation delays, but it's not exactly a language-abstractable concept yet (precisely as it involves the actual hardware gate implementation) in that such black-box simulations estimate average propagation delay as a fixed function dependent upon results obtained from testing specific functionality blocks in specific devices specific gate-counts away from I/O pins, etc. It would be highly desirable to have HDL level modeling of this stuff in the abstract sense, although I confess to not knowing how that could possibly work, given the above.