[xvilka]

Both Verilog and VHDL are a poor fit for chip design. This is why there are so many projects of higher-level hardware description languages. Chisel[1] looks to me as the best one. What I particularly like - they created an intermediate language FIRRTL[2], which might become an LLVM of hardware design. While the exact syntax might be opinionated and we need different options, the fewer wheels reinvented - the better. So at some point, it is important to create the low-level framework, on top of which many different languages can be built. You can read discussion about this particular idea here[3].

[1] https://chisel.eecs.berkeley.edu/

[2] https://bar.eecs.berkeley.edu/projects/firrtl.html

[3] https://github.com/SymbiFlow/ideas/issues/19