[neilv]

The author's stated motivations sounded plausible to me:

> Fairylog is a Racket language (of course) which aims to be quite like Verilog, with less redundant syntax, Racket macros, and several additional compile-time features that Verilog seems to be lacking. > Fairylog extends Racket rather than replaces it, which means you can use all of Racket wherever you like in Fairylog code to help you generate stuff.

I think there might be an additional benefit of this, to implementers of languages atop Racket, in that they can transform/generate syntax objects (essentially, ASTs with source location info) to use this language as backend, pretty easily. I suppose this might be good for rapid experimenting in developing/compiling for CPU+FPGA targets.