[jeanmichelx]

I'm so jealous of software development tools.

Elaborating the hardware (systemverilog) I'm working on (about a year of work from scratch, nothing fancy) takes 8 minutes.

[jtms]

Wow, I get frustrated and feel unproductive if my feedback loop is longer than 2-5 SECONDS. This must require a seriously different approach to trial and error exploration

[dimfeld]

A lot of that is done in a simulator on the computer, which usually builds very quick once you get the environment and simulation scripts written.

The full build to a bit file that can be loaded into hardware is an NP-hard optimization problem, so as your design approaches the limits of either the desired clock speed or the amount of space in the chip, it can become very slow.

[jeanmichelx]

I wish. This figure is reloading the formal tool after a one line change in the RTL.

Placing (not routing!) takes around 24 hours since we need to run in a larger environment than just the block level to get realistic timing reports