[wtallis]

The problem is that any given PCIe root complex does not necessarily support operating those lanes grouped into an arbitrary number of PCIe ports. When you have an x16 group of lanes coming off a CPU, it usually supports operating as x16, x8+x8, and x8+x4+x4, with the latter two requiring some help from the motherboard to re-route lanes. Operating as x4+x4+x4+x4 is usually not possible on consumer-grade CPUs. I'm not aware of any CPU that supports splitting an x4 down to x2+x2.

The Southbridge/PCH on the motherboard is at heart a PCIe fan-out switch that is designed to offer bifurcation down to x2 and x1 ports, but on the flip side doesn't support aggregating lanes into ports wider than x4 (which is the width of the host connection to the CPU).

There are already plenty of low-end NVMe drives that use x2 connections instead of x4. If you put them into a PCIe port that's coming directly off the CPU, you'll have at least two lanes rendered unusable.

Intel has a SSD coming soon that is essentially two x2 drives on a single x4 M.2 card (one with 3D XPoint memory and one with QLC NAND flash memory). I'm expecting this to only be fully functional when attached to the PCH or another PCIe switch that supports bifurcation down to x2. When attached to a CPU PCIe port, I expect only one half of the drive to be accessible.

The bifurcation limitations of CPU PCIe ports may end up changing as PCIe 4.0 and 5.0 make their way to the market, and make SSDs with x1 and x2 connections more viable.