[qalmakka]

During my short experience with hardware design at the university I never had the chance of using Verilog. Are there advantages in using it instead of VHDL?

[Cyph0n]

In my experience, it's:

1) Less verbose and easier to write, but slightly more "error" prone (think: Java vs. Python).

2) More widely used in industry. VHDL is more heavily used in the defense industry (it came out of DoD).

3) Better support for verification (e.g., SystemVerilog).

[q3k]

Open-Source tooling support (Yosys/NextPNR flow, Yosys formal verification flow, Verilator, IVerilog).

VHDL only has GHDL. And there's a bunch of small projects to translate synthesizable VHDL into Verilog (to then feed into the aforementioned tooling), but none of them are good.