[analognoise]

Verilator has some serious limitations:

  The driving test bench is C/C++
  It is a cycle simulator, not a delta-time simulator: it will 
  only simulate synthesizable code (not test bench code) 
  It cannot do back-annotated timing simulations
  It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example)
  It has no mixed-HDL language capabilities
  It requires Gtkwave to view waveforms with (opinion, but I hate the UI)

It is a terrible recommendation for beginners - you'd be much better served by using Xilinx Vivado's inbuilt simulator and waveform viewer.

[orbifold]

It has a steep learning curve, but overall I think it forces you to adopt good development practices from the start. Since it generates C++ you can also easily wrap that code and expose it to python. That way you can use software tools instead of system verilog and can easily do integration testing with your software HAL. In practice our group uses commercial tools (synopsis, cadence) and DPI-C but for the most part this is because of the VHDL code we have. Vivado‘s build in simulator is way too slow.

[q3k]

The first two are a feature for me. Not to mention not being crippled by Xilinx 'IP Core' DRM.

[analognoise]

Crippled by extant, available code which is shipping in millions of devices?

Is it perfect? Hell no. But it's a bit drastic to throw out an entire catalog of the most battle-tested HDL code in the world, isn't it?

[_chris_]

> It requires Gtkwave to view waveforms with (opinion, but I hate the UI)

It dumps a value-change file (vcd) which can be viewed by anything, no? Sure it's not very compressed (and the compile-time for vcd-generation is unfortunate), but it's not a show-stopper.

[analognoise]

This is correct; although I am unaware of a FOSS vcd viewer which improves upon Gtkwave.

I would be exceedingly happy to find one, however; please let me know.