[ZirconiumX]

So, I consider myself a MIPS fan, having studied the early (SGI era) MIPS revisions, but if I started from a clean sheet, I would pick RISC-V over MIPS, because while MIPS is a fairly clean architecture, RISC-V is cleaner.

For example, the MIPS R4000 CPU had three microarchitectural branch delay slots of which the latter two had to be cancelled, and that must have been awkward to design.

In contrast, RISC-V has no ISA branch delay slots, so requires less from lower-end implementations, and provides more to higher-end out-of-order CPUs.

[analognoise]

The OpenMIPS initiative is targeting the 32 and 64-bit MIPS Instruction Set Architecture, Release 6 - I'm unsure if the branch delay slot mess is present in it.

Hopefully someone can chime in with the answer.