[daeken]

I'm also curious as to how this will interact with system memory and IO. Not many details, but I can't help but be insanely excited -- this opens up so many possibilities in terms of crypto... not to mention the demoscene!

Edit: Just got the product brief. Some more info on the FPGA:

> Features transceiver speeds up to 3.125 Gbps, high-speed LVDS with SERDES at up to 840 Mbps, support for DDR3, DDR2, DDR SDRAM, QDR II, and QDR II+ SRAM memory interfacing, up to four general-purpose PLLs, 312 18 x 18 multipliers and more than 60,000 logic elements and 350 user I/O pins. Each of the high-speed transceiver channels have a clock data recovery (CDR) feature, and support for multiple I/O standards such as 3.3-V LVTTL/3.3-V LVCMOS, single-ended SSTL/HSTL and differential SSTL/HSTL.