[twtw]

Sure, and the article discusses that. I was thinking at the instruction level. I tend to think of convincing the hardware to do what you want and convincing the compiler to do what you want separately as an effect of writing code before the languages had specified memory models.

EDIT: Though as I think about it I'm having a hard time thinking of a system in which those compiler optimizations are problematic on a uniprocessor system. It is definitely true that optimizations that are safe on a uniprocessor break on a multiprocessor, but I can't think of any systems that don't (effectively) have a memory barrier when switching between threads. SMT wouldn't see a problem because both threads are on the same processor.

[firethief]

Imagine implementing a simple spinlock, but then substituting relaxed atomics for acquire/release synchronization. The compiler can reorder taking the lock relative to the protected operations and render the lock useless.

[twtw]

Thanks!