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by jawnv6
2686 days ago
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a memory fence is not required, as per my reading of the Intel documentation. i think you're just guessing and haven't actually written any SMC x86? would you mind sharing what PRM sections back up this reading? maybe a careful re-read will help you figure out what "might" require a full fence. |
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I'm generally willing to hold a technical discussion among peers. But it has to be on even terms with a decent amount of respect given both ways. Your tone in the post above, as well as your posting history, does not give me any hope towards having a good discussion with you.