[pedroaraujo]

1. Verilog requires semicolons almost everywhere. Can you point to a specific example?

2. Are we talking about Verilog or SystemVerilog? Verilog is not suitable for functional verification, people usually use SystemVerilog and methodologies like UVM for verification.

3. It's hard to tell what your college did exactly but it sounds like he over-engineer something himself.

You are talking about the advantages of Chisel for functional verification, not for hardware design, which was exactly the point I was trying to make.

[uxp100]

RE: #3 I think Perl for Verilog metaprogramming is pretty common, but I'm not really sure, have rarely written the stuff myself. But I've seen it before.

[dnautics]

It's an intel thing, apparently.