[eBombzor]

Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp

For actually learning RISC-V, you can check out these books: https://riscv.org/risc-v-books/

The Patterson and Hennessy book is a great starting point and the RISC-V reader is great reference.

[sitkack]

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense.

https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch...

https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel)

https://github.com/ucb-bar/riscv-sodor (Chisel)

https://chisel.eecs.berkeley.edu/

[eBombzor]

Yup I'm an idiot but I can't seem to delete or edit my original submission :c

Thank you for the information.

[sitkack]

Ur good. Chisel.

[dooglius]

> Since RISC-V uses Chisel instead of Verilog

What do you mean? The core here is entirely Verilog/SystemVerilog

[mepian]

I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.

[eBombzor]

Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?

[yjftsjthsd-h]

Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)

[chrisseaton]

> Since RISC-V uses Chisel instead of Verilog

How can an ISA ‘use Chisel’? It’s a spec not an implementation.